1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device and, more particularly, to a method of fabricating a metal-insulator-metal capacitor.
2. Description of Related Art
Metal interconnections are employed in the fabrication of semiconductor devices. The metal interconnections should have low electrical resistance and high reliability in order to realize high performance of semiconductor devices. Copper interconnections are very attractive because such interconnections exhibit low electrical resistance and high reliability. However, it is difficult to form copper interconnections using a conventional photolithography/etching process. Thus, a damascene process is widely used in formation of the copper interconnections. A damascene process is a process of embedding a metal conductor pattern in a dielectric film on a substrate, which results in a planar interconnection layer.
Most semiconductor devices comprise transistors, resistors and capacitors. Each capacitor is composed of a top electrode and a bottom electrode that overlap each other and a dielectric layer interposed between the top and bottom electrodes. The electrodes may be formed of a doped polysilicon layer. However, the polysilicon layer can be oxidized during a subsequent thermal process. Accordingly, electrical characteristics of the capacitor may be changed. In addition, the capacitor may exhibit non-uniform characteristics with respect to the magnitude of voltage applied to the polysilicon electrode. For example, if the top and bottom electrodes are formed of an N-type polysilicon layer and a negative voltage is applied to the top electrode, holes are induced at the surface of the bottom electrode. Thus, a depletion layer may be formed at the surface of the bottom electrode. A width of the depletion layer varies according to the magnitude of the negative voltage. As a result, the capacitance may be not be uniform depending on the magnitudes of the voltages applied to the electrodes. Therefore, the capacitor employing the polysilicon electrodes is inadequate for a semiconductor device that needs uniform characteristics, for example an analog circuit device.
A capacitor having metal electrodes, e.g., a metal-insulator-metal (MIM) capacitor has been proposed in order to solve the above-mentioned problems. The MIM capacitor is discussed in U.S. Pat. No. 6,259,128 to Adler et al., entitled “Metal-Insulator-Metal Capacitor For Copper Damascene Process And Method Of Forming The Same.”
FIGS. 1 and 2 are cross sectional views for illustrating a known method of fabricating the MIM capacitor.
Referring to FIG. 1, an interlayer insulating layer 3 is formed on a semiconductor substrate 1. A first copper interconnection line 5a and a second copper interconnection line 5b are formed in the interlayer insulating layer 3 using a conventional damascene technique. A silicon nitride layer 7 is formed on the substrate 1 having the first and second copper interconnection lines 5a and 5b, and the silicon nitride layer 7 is patterned to expose the first copper interconnection line 5a. A first lower barrier layer 9, a bottom electrode layer 11, a first upper barrier layer 13, a dielectric layer 15, a second lower barrier layer 17, a top electrode layer 19 and a second upper barrier layer 21 are sequentially formed on the substrate 1 including the patterned silicon nitride layer 7. A photoresist pattern 23 is then formed on the second upper barrier layer 21. The photoresist pattern 23 is formed over the first copper interconnection line 5a. 
Referring to FIG. 2, the second upper barrier layer 21, the top electrode layer 19, the second lower barrier layer 17, the dielectric layer 15, the first upper barrier layer 13, the bottom electrode layer 11 and the first lower barrier layer 9 are successively etched using the photoresist pattern 23 as an etching mask, thereby forming an MIM capacitor 25 electrically connected to the first copper interconnection line 5a. The etching process for forming the MIM capacitor 25 is performed using a wet etching technique. As a result, the MIM capacitor 25 is composed of a first lower barrier layer pattern 9a, a bottom electrode 11a, a first upper barrier layer pattern 13a, a dielectric layer pattern 15a, a second lower barrier layer pattern 17a, a top electrode 19a and a second upper barrier layer pattern 21a, which are sequentially stacked, as shown in FIG. 2.
The photoresist pattern 23 is removed using an ashing process. The ashing process is performed using oxygen plasma. Generally, the ashing process is followed by a wet strip process for removing photoresist residue and polymers. The wet strip process is carried out using a chemical solution containing hydrofluoric acid (HF). However, in the event that the MIM capacitor 25 is patterned using the wet etching technique as mentioned above, polymers are not generated. Thus, the wet strip process may not be required after the ashing process for removing the photoresist pattern 23.
If a dry etching technique using plasma is employed instead of the wet etching technique, the patterned silicon nitride layer 7 on the second copper interconnection line 5b may be damaged. As a result, pits may be formed in regions of the patterned silicon nitride layer 7 that may expose regions of the second copper interconnection line 5b. In this case, if the ashing process is applied in order to remove the photoresist pattern 23, the exposed regions of the second copper interconnection line 5b may be oxidized. The oxidation of the second copper interconnection line 5b results in a volume expansion thereof. Accordingly, the oxidized regions of the second copper interconnection line 5b upwardly protrude through the pits. After the ashing process, the wet strip process should be performed in order to remove polymers generated during the dry etching process. The oxidized regions of the second copper interconnection line 5b are removed during the wet strip process. As a result, voids are formed in the second copper interconnection line 5b, thereby degrading reliability of the second copper interconnection line 5b. 
Therefore, the patterning process for forming the MIM capacitor 25 may be performed using the wet etching technique so as to avoid the disadvantages of dry etching.
However, four layers of barrier material, two layers of electrode material and one layer of dielectric material are patterned using the wet etching technique. Thus, various kinds of wet etching solutions are required in order to form the MIM capacitor 25. As a result, the burden on the photoresist pattern is increased during the wet etching process and the photoresist pattern may be displaced or deformed during the wet etching process. Accordingly, there exists a need for a method of fabricating an MIM capacitor that reduces the burden on the photoresist pattern during wet etching.